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| author | Daniel Vetter | 2014-11-20 09:26:30 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2014-11-20 13:03:33 +0100 |
| commit | 656bfa3afc14e45e2d9e1624bf60d79b3beb12f2 (patch) | |
| tree | c71479a78a33330ae9692e4e2504d914405d5030 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Update ring freq for full gpu freq range (diff) | |
| download | kernel-qcow2-linux-656bfa3afc14e45e2d9e1624bf60d79b3beb12f2.tar.gz kernel-qcow2-linux-656bfa3afc14e45e2d9e1624bf60d79b3beb12f2.tar.xz kernel-qcow2-linux-656bfa3afc14e45e2d9e1624bf60d79b3beb12f2.zip | |
drm/i915: Pin tiled objects for L-shaped configs
Let's just throw in the towel on this one and take the cheap way out.
Based on a patch from Chris Wilson, but checking for a different bit.
Chris' patch checked for even bank layout, this one here for a magic
bit. Given the evidence we've gathered (not much) both work I think,
but checking for the magic bit might be more accurate.
Anyway, works on my gm45 here.
For paranoi restrict to gen4 (and mobile), since we've only ever seen
this on gm45 and i965gm.
Also add some debugfs output so that we can skip the tiled swapping
tests properly in these cases.
v2: Clean up the quirk'ed pin count in free_object to avoid upsetting
the WARN_ON. Spotted by Chris.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28813
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45092
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3a51c05ca552..3102907a96a7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2043,6 +2043,8 @@ enum punit_power_well { #define DCC_ADDRESSING_MODE_MASK (3 << 0) #define DCC_CHANNEL_XOR_DISABLE (1 << 10) #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) +#define DCC2 0x10204 +#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) /* Pineview MCH register contains DDR3 setting */ #define CSHRDDR3CTL 0x101a8 |