diff options
| author | A.Sunil Kamath | 2014-11-24 09:07:44 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2015-04-16 09:20:16 +0200 |
| commit | 664326f8a5b7e4ab7ed469acaadc63d2a05d8720 (patch) | |
| tree | d9443c305b7e13faa3db6a1e1f368aff2f44475a /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/bxt: add description about the BXT PHYs (diff) | |
| download | kernel-qcow2-linux-664326f8a5b7e4ab7ed469acaadc63d2a05d8720.tar.gz kernel-qcow2-linux-664326f8a5b7e4ab7ed469acaadc63d2a05d8720.tar.xz kernel-qcow2-linux-664326f8a5b7e4ab7ed469acaadc63d2a05d8720.zip | |
drm/i915/bxt: Implement enable/disable for Display C9 state
v2: Modified as per review comments from Imre
- Mention enabling instead of allowing in the debug trace and
remove unnecessary comments.
v3:
- Rebase to latest.
- Move DC9-related functions from intel_display.c to intel_runtime_pm.c.
v4: (imre)
- remove DC5 disabling, it's a nop at this point
- squashed in Suketu's "Assert the requirements to enter or exit DC9"
patch
- remove check for RUNTIME_PM from assert_can_enable_dc9, it's not a
dependency
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> (v3)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 11b9a0898111..29c41f1bba34 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7059,6 +7059,11 @@ enum skl_disp_power_wells { #define BXT_DE_PLL_PLL_ENABLE (1 << 31) #define BXT_DE_PLL_LOCK (1 << 30) +/* GEN9 DC */ +#define DC_STATE_EN 0x45504 +#define DC_STATE_EN_UPTO_DC5 (1<<0) +#define DC_STATE_EN_DC9 (1<<3) + /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, * since on HSW we can't write to it using I915_WRITE. */ #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) |