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| author | Ville Syrjälä | 2015-05-05 16:06:20 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2015-06-15 11:27:59 +0200 |
| commit | 6d67415f40b1f166212f37ecc9c23b9f380dfebc (patch) | |
| tree | de375437bc6232f273781acda97d7d251c230817 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Implement WaEnableHDMI8bpcBefore12bpc:snb, ivb (diff) | |
| download | kernel-qcow2-linux-6d67415f40b1f166212f37ecc9c23b9f380dfebc.tar.gz kernel-qcow2-linux-6d67415f40b1f166212f37ecc9c23b9f380dfebc.tar.xz kernel-qcow2-linux-6d67415f40b1f166212f37ecc9c23b9f380dfebc.zip | |
drm/i915: Send GCP infoframes for deep color HDMI sinks
GCP infoframes are required to inform the HDMI sink about the color
depth.
Send the GCP infoframe whenever the sink supports any deep color modes
since such sinks must anyway be capable of receiving them. For sinks
that don't support deep color let's skip the GCP in case it might
confuse the sink, although HDMI 1.4 spec does say all sinks must be
capable of reciving them. In theory we could skip the GCP infoframe
for deep color sinks in 8bpc mode as well since sinks must fall back to
8bpc whenever GCP isn't received for some time.
BSpec says we should disable GCP after disabling the port, so do that as
well.
v2: s/intel_set_gcp_infoframe/intel_hdmi_set_gcp_infoframe/
Rebased due to crtc->config changes
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Resolve conflict with lack of chv phy patches and fixup typo
Chandra spotted.]
Reviewed-by: Chandra Konduru <Chandra.konduru@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1db6b4bf68fd..c9f9d3d3adba 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6061,6 +6061,9 @@ enum skl_disp_power_wells { #define _VIDEO_DIP_CTL_A 0xe0200 #define _VIDEO_DIP_DATA_A 0xe0208 #define _VIDEO_DIP_GCP_A 0xe0210 +#define GCP_COLOR_INDICATION (1 << 2) +#define GCP_DEFAULT_PHASE_ENABLE (1 << 1) +#define GCP_AV_MUTE (1 << 0) #define _VIDEO_DIP_CTL_B 0xe1200 #define _VIDEO_DIP_DATA_B 0xe1208 |