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| author | Mika Kuoppala | 2015-10-30 16:54:47 +0100 |
|---|---|---|
| committer | Ville Syrjälä | 2015-11-09 18:16:19 +0100 |
| commit | 6fb403de3620deacf1180d727d21875d07c7464a (patch) | |
| tree | 01bbf9680726f4b322b3e26f9a9d0c54bb251389 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/bxt: Expose DC5 entry count (diff) | |
| download | kernel-qcow2-linux-6fb403de3620deacf1180d727d21875d07c7464a.tar.gz kernel-qcow2-linux-6fb403de3620deacf1180d727d21875d07c7464a.tar.xz kernel-qcow2-linux-6fb403de3620deacf1180d727d21875d07c7464a.zip | |
drm/i915: Add csr programming registers to dmc debugfs entry
We check these to determine firmware loading status. Include
them to help to debug causes of firmware loading fails.
v2: Move all CSR specific registers to i915_reg.h (Ville)
v3: Rebase
v4: Rebase (RPM ref)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446220487-32691-1-git-send-email-mika.kuoppala@intel.com
Tested-by: Daniel Stone <daniels@collabora.com> # SKL
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 083991271060..2183a6e1f134 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5698,6 +5698,16 @@ enum skl_disp_power_wells { #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* DMC/CSR */ +#define CSR_PROGRAM(i) (0x80000 + (i) * 4) +#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 +#define CSR_HTP_ADDR_SKL 0x00500034 +#define CSR_SSP_BASE 0x8F074 +#define CSR_HTP_SKL 0x8F004 +#define CSR_LAST_WRITE 0x8F034 +#define CSR_LAST_WRITE_VALUE 0xc003b400 +/* MMIO address range for CSR program (0x80000 - 0x82FFF) */ +#define CSR_MMIO_START_RANGE 0x80000 +#define CSR_MMIO_END_RANGE 0x8FFFF #define SKL_CSR_DC3_DC5_COUNT 0x80030 #define SKL_CSR_DC5_DC6_COUNT 0x8002C #define BXT_CSR_DC3_DC5_COUNT 0x80038 |