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| author | Daniel Vetter | 2013-11-01 10:50:21 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2013-11-01 18:23:41 +0100 |
| commit | 8409360381ebaaab82c7ab502665a29423fcdfc2 (patch) | |
| tree | cdd4b8699043f6757e94df3313e5f01a4affa974 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i916: add "auto" pipe CRC source (diff) | |
| download | kernel-qcow2-linux-8409360381ebaaab82c7ab502665a29423fcdfc2.tar.gz kernel-qcow2-linux-8409360381ebaaab82c7ab502665a29423fcdfc2.tar.xz kernel-qcow2-linux-8409360381ebaaab82c7ab502665a29423fcdfc2.zip | |
drm/i915: scramble reset support for DP port CRC on g4x
We need to reset the DP scrambler on every vsync to get stable CRCs.
And since we can't use the normal pipe CRC on DP ports on g4x we
really need them to be able to test modesetting issues on (e)DP
outputs.
Note that the DC balance reset is for SDVO port CRCs so we don't
strictly need it. But better safe than sorry (and it's a nice template
in case we ever want to grab port CRCs for e.g. audio checking).
v2: Apply the suggestions from Damien's review.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3dfcac7ef3c4..4328e3bd63b2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2150,6 +2150,14 @@ #define PCH_HDMIC 0xe1150 #define PCH_HDMID 0xe1160 +#define PORT_DFT_I9XX 0x61150 +#define DC_BALANCE_RESET (1 << 25) +#define PORT_DFT2_G4X 0x61154 +#define DC_BALANCE_RESET_VLV (1 << 31) +#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) +#define PIPE_B_SCRAMBLE_RESET (1 << 1) +#define PIPE_A_SCRAMBLE_RESET (1 << 0) + /* Gen 3 SDVO bits: */ #define SDVO_ENABLE (1 << 31) #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) |