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| author | Eric Anholt | 2010-03-18 21:21:14 +0100 |
|---|---|---|
| committer | Eric Anholt | 2010-03-19 00:48:01 +0100 |
| commit | 8956c8bba5b11b3d3aec000e6c6184943011a8d4 (patch) | |
| tree | e3e712d6c58108b8937827f5c3cdecc3ae8f5afc /drivers/gpu/drm/i915/i915_reg.h | |
| parent | agp/intel: Don't do the chipset flush on Sandybridge. (diff) | |
| download | kernel-qcow2-linux-8956c8bba5b11b3d3aec000e6c6184943011a8d4.tar.gz kernel-qcow2-linux-8956c8bba5b11b3d3aec000e6c6184943011a8d4.tar.xz kernel-qcow2-linux-8956c8bba5b11b3d3aec000e6c6184943011a8d4.zip | |
drm/i915: Set up the documented clock gating on Sandybridge and Ironlake.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2720bc2cd678..cbbf59f56dfa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2176,6 +2176,14 @@ #define DISPLAY_PORT_PLL_BIOS_1 0x46010 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 +#define PCH_DSPCLK_GATE_D 0x42020 +# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) +# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) + +#define PCH_3DCGDIS0 0x46020 +# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) +# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) + #define FDI_PLL_FREQ_CTL 0x46030 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |