summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/i915_reg.h
diff options
context:
space:
mode:
authorRodrigo Vivi2017-08-16 01:16:48 +0200
committerRodrigo Vivi2017-08-19 00:32:17 +0200
commit90007bca61627bb2fbd63bc3da0277abe4a43550 (patch)
treed3bd317a361083833f7f3b7452d81bdb906c0524 /drivers/gpu/drm/i915/i915_reg.h
parentdrm/i915: Clear lost context-switch interrupts across reset (diff)
downloadkernel-qcow2-linux-90007bca61627bb2fbd63bc3da0277abe4a43550.tar.gz
kernel-qcow2-linux-90007bca61627bb2fbd63bc3da0277abe4a43550.tar.xz
kernel-qcow2-linux-90007bca61627bb2fbd63bc3da0277abe4a43550.zip
drm/i915/cnl: Introduce initial Cannonlake Workarounds.
Let's inherit workarounds from previous platforms that according to wa_database and BSpec are still valid for Cannonlake. v2: Add missed workarounds. v3: Rebase v4: Remove bad chunk that was added to rc6 disable. (Ander) Also remove A0 W/a that are not needed anymore. v5: Rebase on top of CFL. v6: Remove empty gen9_init_perctx_bb and gen9_init_indirectctx_bb since they don't carry any gen10 related W/a. (by Oscar). Also Remove A0 exclusive workaround. v7: Remove more A0 exclusive workarounds. As pointed out by Oscar many workarounds were changed to be A0 only so let's remove them. Cc: Oscar Mateo <oscar.mateo@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170815231651.975-1-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ed7cd9ee2c2a..2dcae9f24a85 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3807,6 +3807,12 @@ enum {
#define PWM1_GATING_DIS (1 << 13)
/*
+ * GEN10 clock gating regs
+ */
+#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
+#define SARBUNIT_CLKGATE_DIS (1 << 5)
+
+/*
* Display engine regs
*/