diff options
| author | Ville Syrjälä | 2014-04-09 12:29:05 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-06-11 16:57:29 +0200 |
| commit | 9197c88bf946cf792ad5124f00bd51a0bc18f8c2 (patch) | |
| tree | fc3f7a0357006194bd7b7dd06ba59f7bc249f22b /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/chv: Freq(opcode) request for CHV. (diff) | |
| download | kernel-qcow2-linux-9197c88bf946cf792ad5124f00bd51a0bc18f8c2.tar.gz kernel-qcow2-linux-9197c88bf946cf792ad5124f00bd51a0bc18f8c2.tar.xz kernel-qcow2-linux-9197c88bf946cf792ad5124f00bd51a0bc18f8c2.zip | |
drm/i915/chv: Try to program the PHY used clock channel overrides
These should make it possible to feed port C from pipe A or port B from
pipe B. Didn't quite seem to work though.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 53db3a2db3df..fd541fc7d70d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -771,6 +771,8 @@ enum punit_power_well { #define _VLV_PCS_DW8_CH0 0x8220 #define _VLV_PCS_DW8_CH1 0x8420 +#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) +#define CHV_PCS_USEDCLKCHANNEL (1 << 21) #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) #define _VLV_PCS01_DW8_CH0 0x0220 @@ -895,6 +897,11 @@ enum punit_power_well { #define DPIO_DCLKP_EN (1 << 13) #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) +#define _CHV_CMN_DW19_CH0 0x814c +#define _CHV_CMN_DW6_CH1 0x8098 +#define CHV_CMN_USEDCLKCHANNEL (1 << 13) +#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) + #define CHV_CMN_DW30 0x8178 #define DPIO_LRC_BYPASS (1 << 3) |