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| author | Rodrigo Vivi | 2013-08-28 21:45:46 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2013-09-04 17:34:51 +0200 |
| commit | 9435373ef8870e0a84b6fec0ad89b952bf3097fa (patch) | |
| tree | b3dc336376cce918843d011068107b2bd73a63c9 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/dsi: s/size_t/int/ (diff) | |
| download | kernel-qcow2-linux-9435373ef8870e0a84b6fec0ad89b952bf3097fa.tar.gz kernel-qcow2-linux-9435373ef8870e0a84b6fec0ad89b952bf3097fa.tar.xz kernel-qcow2-linux-9435373ef8870e0a84b6fec0ad89b952bf3097fa.zip | |
drm/i915: Report enabled slices on Haswell GT3
Batchbuffers constructed by userspace can conditionalise their URB
allocations through the use of the MI_SET_PREDICATE command. This
command can read the MI_PREDICATE_RESULT_2 register to see how many
slices are enabled on GT3, and by virtue of the result, scale their
memory allocations to fit enabled memory.
Of course, this only works if the kernel sets the appropriate bit in the
register first.
v2: Better commit subject and message by Chris Wilson.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Credits-to: Yejun Guo <yejun.guo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f626a16a14fa..c7f2da36f4a8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -264,6 +264,11 @@ #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ #define MI_SEMAPHORE_SYNC_INVALID (3<<16) + +#define MI_PREDICATE_RESULT_2 (0x2214) +#define LOWER_SLICE_ENABLED (1<<0) +#define LOWER_SLICE_DISABLED (0<<0) + /* * 3D instructions used by the kernel */ |