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| author | Paulo Zanoni | 2014-07-04 16:59:58 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-07-10 08:27:09 +0200 |
| commit | 9ccd5aeb2901aaaabf77f185e2e5ea3a0b577e86 (patch) | |
| tree | 201f29314c86977797f72c8c9e844860862d7082 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: fix hsw_write_dcomp() error message (diff) | |
| download | kernel-qcow2-linux-9ccd5aeb2901aaaabf77f185e2e5ea3a0b577e86.tar.gz kernel-qcow2-linux-9ccd5aeb2901aaaabf77f185e2e5ea3a0b577e86.tar.xz kernel-qcow2-linux-9ccd5aeb2901aaaabf77f185e2e5ea3a0b577e86.zip | |
drm/i915: fix D_COMP usage on BDW
On HSW, the D_COMP register can be accessed through the mailbox (read
and write) or through MMIO on a MCHBAR offset (read only). On BDW, the
access should be done through MMIO on another address. So to account
for all these cases, create hsw_read_dcomp() with the correct
implementation for reading, and also fix hsw_write_dcomp() to do the
correct thing on BDW.
With this patch, we can now get back from the PC8+ state on BDW. We
were previously getting a black screen and lots of dmesg errors.
Please notice that the bug only happens when you actually reach the
PC8+ states, not when you only allow it.
Testcase: igt/pm_rpm/rte
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 190d4bb5ad53..a2117a98c3df 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5984,7 +5984,10 @@ enum punit_power_well { #define LCPLL_CD_SOURCE_FCLK (1<<21) #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) -#define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) +/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, + * since on HSW we can't write to it using I915_WRITE. */ +#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) +#define D_COMP_BDW 0x138144 #define D_COMP_RCOMP_IN_PROGRESS (1<<9) #define D_COMP_COMP_FORCE (1<<8) #define D_COMP_COMP_DISABLE (1<<0) |