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| author | Gaurav K Singh | 2014-12-05 09:43:41 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2014-12-05 15:28:20 +0100 |
| commit | a9da9bce88ee842c7904b5670c035ca759e77238 (patch) | |
| tree | d5a078e15b1db6eaf2ae49570ae5acb7cd9b0e80 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Add support for port enable/disable for dual link configuration (diff) | |
| download | kernel-qcow2-linux-a9da9bce88ee842c7904b5670c035ca759e77238.tar.gz kernel-qcow2-linux-a9da9bce88ee842c7904b5670c035ca759e77238.tar.xz kernel-qcow2-linux-a9da9bce88ee842c7904b5670c035ca759e77238.zip | |
drm/i915: Pixel Clock changes for DSI dual link
For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.
v2 : Address review comments by Jani
- Removed the bit mask used for ->dual_link
- Used DSI instead of MIPI for #define variables
v3: Added the VLV_DISPLAY_BASE to VLV_CHICKEN_3 register
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b4a11ab7cb63..869e5ae1b011 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6030,6 +6030,10 @@ enum punit_power_well { #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) #define VLV_PWRDWNUPCTL 0xA294 +#define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C) +#define PIXEL_OVERLAP_CNT_MASK (3 << 30) +#define PIXEL_OVERLAP_CNT_SHIFT 30 + #define GEN6_PMISR 0x44020 #define GEN6_PMIMR 0x44024 /* rps_lock */ #define GEN6_PMIIR 0x44028 |