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| author | Imre Deak | 2017-07-11 22:42:35 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2017-07-27 09:38:53 +0200 |
| commit | b2891eb2531e5e0d251febd0a395d758111790d4 (patch) | |
| tree | 122b5d0206a9ce94ffd9a2b5935fadc5371a20bf /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/hsw, bdw: Wait for the power well disabled state (diff) | |
| download | kernel-qcow2-linux-b2891eb2531e5e0d251febd0a395d758111790d4.tar.gz kernel-qcow2-linux-b2891eb2531e5e0d251febd0a395d758111790d4.tar.xz kernel-qcow2-linux-b2891eb2531e5e0d251febd0a395d758111790d4.zip | |
drm/i915/hsw+: Add has_fuses power well attribute
The pattern of a power well backing a set of fuses whose initialization
we need to wait for during power well enabling is common to all GEN9+
platforms. Adding support for this to the HSW power well enable helper
allows us to use the HSW/BDW power well code for GEN9+ as well in a
follow-up patch.
v2:
- Use an enum for power gates instead of raw numbers. (Ville)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-6-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d7241a25a929..c83f1095cb21 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8023,11 +8023,17 @@ enum { #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) /* SKL Fuse Status */ +enum skl_power_gate { + SKL_PG0, + SKL_PG1, + SKL_PG2, +}; + #define SKL_FUSE_STATUS _MMIO(0x42000) -#define SKL_FUSE_DOWNLOAD_STATUS (1<<31) -#define SKL_FUSE_PG0_DIST_STATUS (1<<27) -#define SKL_FUSE_PG1_DIST_STATUS (1<<26) -#define SKL_FUSE_PG2_DIST_STATUS (1<<25) +#define SKL_FUSE_DOWNLOAD_STATUS (1<<31) +/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */ +#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1) +#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 |