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| author | Paulo Zanoni | 2013-05-31 16:45:06 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2013-05-31 20:54:14 +0200 |
| commit | cca32e9ad372172c808b93eebff536459ce37d85 (patch) | |
| tree | 16e386436331a152ff35cb725462ab23c7c45c77 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: properly set HSW WM_PIPE registers (diff) | |
| download | kernel-qcow2-linux-cca32e9ad372172c808b93eebff536459ce37d85.tar.gz kernel-qcow2-linux-cca32e9ad372172c808b93eebff536459ce37d85.tar.xz kernel-qcow2-linux-cca32e9ad372172c808b93eebff536459ce37d85.zip | |
drm/i915: properly set HSW WM_LP watermarks
We were previously only setting the WM_PIPE registers, now we are
setting the LP watermark registers. This should allow deeper PC
states, resulting in power savings.
We're only using 1/2 data buffer partitioning for now.
v2: Merge both hsw_compute_pri_wm_* functions (Ville)
v3: - Simplify hsw_compute_wm_results (Ville)
- Rebase due to changes on the previous patch
v4: Unconfuse wm_lp/level (Ville)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 19021bd8b030..e00422128a0a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3100,6 +3100,10 @@ #define WM3S_LP_IVB 0x45128 #define WM1S_LP_EN (1<<31) +#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ + (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ + ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) + /* Memory latency timer register */ #define MLTR_ILK 0x11222 #define MLTR_WM1_SHIFT 0 |