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| author | Ville Syrjälä | 2015-03-05 20:19:51 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2015-03-17 22:30:15 +0100 |
| commit | cfb41411fce52a8e8b6c1f0bd253d4ca7bfcbd0d (patch) | |
| tree | 9a5470ca7c4044c9ff6d0aa47048e4838888b1b1 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Program PFI credits for VLV (diff) | |
| download | kernel-qcow2-linux-cfb41411fce52a8e8b6c1f0bd253d4ca7bfcbd0d.tar.gz kernel-qcow2-linux-cfb41411fce52a8e8b6c1f0bd253d4ca7bfcbd0d.tar.xz kernel-qcow2-linux-cfb41411fce52a8e8b6c1f0bd253d4ca7bfcbd0d.zip | |
drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV
CHV has a new knob in Punit to select between some memory power savings
modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
enabled, so let's do so in the hopes for moar power savings.
v2: Put the thing into a separate function to avoid churn later
v3: Don't break VLV
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8e29e2a6fe5c..b43de97f12da 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -566,6 +566,9 @@ #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) #define DSPFREQGUAR_SHIFT 14 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) +#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ +#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ +#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) |