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| author | Kelvin Gardiner | 2018-03-16 13:14:51 +0100 |
|---|---|---|
| committer | Mika Kuoppala | 2018-03-20 15:26:46 +0100 |
| commit | d3d57927995f872e5786ff6ae517a6c3e7a94d75 (patch) | |
| tree | 2e79ab60cae79bf981799a048a0be6cfdeb3f255 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11 (diff) | |
| download | kernel-qcow2-linux-d3d57927995f872e5786ff6ae517a6c3e7a94d75.tar.gz kernel-qcow2-linux-d3d57927995f872e5786ff6ae517a6c3e7a94d75.tar.xz kernel-qcow2-linux-d3d57927995f872e5786ff6ae517a6c3e7a94d75.zip | |
drm/i915/icl: Update subslice define for ICL 11
ICL 11 has a greater number of maximum subslices. This patch
reflects this.
v2: GEN11 updates to MCR_SELECTOR (Oscar)
v3: Copypasta error in the new defines (Lionel)
Bspec: 21139
BSpec: 21108
Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com> (v1)
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v1)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180316121456.11577-3-mika.kuoppala@linux.intel.com
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 429de0ad6cd4..699292eae02e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2151,6 +2151,10 @@ enum i915_power_well_id { #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) +#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) +#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf) +#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) +#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7) #define RING_IPEIR(base) _MMIO((base)+0x64) #define RING_IPEHR(base) _MMIO((base)+0x68) /* |