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| author | Oscar Mateo | 2018-05-08 23:29:24 +0200 |
|---|---|---|
| committer | Mika Kuoppala | 2018-05-11 14:54:18 +0200 |
| commit | d65dc3e40b80ab63fb0d70c947558d0f49f912da (patch) | |
| tree | 2582b3bbba2fcc4bae19f611ea553bffa7835cd1 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/icl: Introduce initial Icelake Workarounds (diff) | |
| download | kernel-qcow2-linux-d65dc3e40b80ab63fb0d70c947558d0f49f912da.tar.gz kernel-qcow2-linux-d65dc3e40b80ab63fb0d70c947558d0f49f912da.tar.xz kernel-qcow2-linux-d65dc3e40b80ab63fb0d70c947558d0f49f912da.zip | |
drm/i915/icl: Enable Sampler DFR
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.
v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring
v4: Move to icl_init_clock_gating, since it's not a WA (Rodrigo)
v5: C, not lisp (Chris)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Praveen Paneri <praveen.paneri@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-3-git-send-email-oscar.mateo@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2b22d4d3b0df..6aad16ee44ae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8253,6 +8253,9 @@ enum { #define GEN8_GARBCNTL _MMIO(0xB004) #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7) +#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550) +#define DFR_DISABLE (1 << 9) + /* IVYBRIDGE DPF */ #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) |