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| author | Chris Wilson | 2010-10-01 13:05:06 +0200 |
|---|---|---|
| committer | Chris Wilson | 2010-10-01 15:47:12 +0200 |
| commit | dc96e9b8e37641d9d15a8a4cdd18ed7680d8f546 (patch) | |
| tree | 5d410cf8a1df84a73380d4fad3c76d725b7adee9 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Clear fence registers on GPU reset (diff) | |
| download | kernel-qcow2-linux-dc96e9b8e37641d9d15a8a4cdd18ed7680d8f546.tar.gz kernel-qcow2-linux-dc96e9b8e37641d9d15a8a4cdd18ed7680d8f546.tar.xz kernel-qcow2-linux-dc96e9b8e37641d9d15a8a4cdd18ed7680d8f546.zip | |
drm/i915: Try to reset gen2 devices.
So far only found registers for i830, i845, i865 and one of those has no
effect on i865!
At this moment in time, attempting to reset i8xx is a little
optimistic...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ddbcd8c109e0..58cfea25a645 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -216,6 +216,16 @@ #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ #define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */ + +/* + * Reset registers + */ +#define DEBUG_RESET_I830 0x6070 +#define DEBUG_RESET_FULL (1<<7) +#define DEBUG_RESET_RENDER (1<<8) +#define DEBUG_RESET_DISPLAY (1<<9) + + /* * Fence registers */ @@ -763,6 +773,7 @@ #define DPLLA_TEST_M_BYPASS (1 << 2) #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) #define D_STATE 0x6104 +#define DSTATE_GFX_RESET_I830 (1<<6) #define DSTATE_PLL_D3_OFF (1<<3) #define DSTATE_GFX_CLOCK_GATING (1<<1) #define DSTATE_DOT_CLOCK_GATING (1<<0) |