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| author | Lucas De Marchi | 2018-07-27 21:36:47 +0200 |
|---|---|---|
| committer | Rodrigo Vivi | 2018-08-16 20:52:08 +0200 |
| commit | dce888798d3ed1c7fea2d45f5f757a749a9e2584 (patch) | |
| tree | ac6a569c624606e944d1a5d8382d016b36951d9b /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/gvt: use its own define for gpio (diff) | |
| download | kernel-qcow2-linux-dce888798d3ed1c7fea2d45f5f757a749a9e2584.tar.gz kernel-qcow2-linux-dce888798d3ed1c7fea2d45f5f757a749a9e2584.tar.xz kernel-qcow2-linux-dce888798d3ed1c7fea2d45f5f757a749a9e2584.zip | |
drm/i915: remove confusing GPIO vs PCH_GPIO
Instead of defining all registers twice, define just a PCH_GPIO_BASE
that has the same address as PCH_GPIO_A and use that to calculate all
the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
the same thing.
v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
macro to return a particular gpio address and move the enum out of
i915_reg.h (suggested by Jani)
v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
actually need to be changed (suggested by Daniel/Ville)
v4: Move definition of i915_gpio to intel_display.h and remove
GMBUS/GPIO handling from gvt since now they have their own
defines.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180727193647.8639-3-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 24 |
1 files changed, 5 insertions, 19 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 14b47f431a23..5121b9f072c6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3082,18 +3082,9 @@ enum i915_power_well_id { /* * GPIO regs */ -#define GPIOA _MMIO(0x5010) -#define GPIOB _MMIO(0x5014) -#define GPIOC _MMIO(0x5018) -#define GPIOD _MMIO(0x501c) -#define GPIOE _MMIO(0x5020) -#define GPIOF _MMIO(0x5024) -#define GPIOG _MMIO(0x5028) -#define GPIOH _MMIO(0x502c) -#define GPIOJ _MMIO(0x5034) -#define GPIOK _MMIO(0x5038) -#define GPIOL _MMIO(0x503C) -#define GPIOM _MMIO(0x5040) +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ + 4 * (gpio)) + # define GPIO_CLOCK_DIR_MASK (1 << 0) # define GPIO_CLOCK_DIR_IN (0 << 1) # define GPIO_CLOCK_DIR_OUT (1 << 1) @@ -7489,6 +7480,8 @@ enum { /* PCH */ +#define PCH_DISPLAY_BASE 0xc0000u + /* south display engine interrupt: IBX */ #define SDE_AUDIO_POWER_D (1 << 27) #define SDE_AUDIO_POWER_C (1 << 26) @@ -7783,13 +7776,6 @@ enum { #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) -#define PCH_GPIOA _MMIO(0xc5010) -#define PCH_GPIOB _MMIO(0xc5014) -#define PCH_GPIOC _MMIO(0xc5018) -#define PCH_GPIOD _MMIO(0xc501c) -#define PCH_GPIOE _MMIO(0xc5020) -#define PCH_GPIOF _MMIO(0xc5024) - #define _PCH_DPLL_A 0xc6014 #define _PCH_DPLL_B 0xc6018 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |