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| author | Imre Deak | 2016-08-10 13:07:31 +0200 |
|---|---|---|
| committer | Imre Deak | 2016-08-10 15:00:47 +0200 |
| commit | ed6143b8f7537db98e94feeb50e7b7f698c7cb05 (patch) | |
| tree | a28f91f34ae2ee76200645a5c80c2743783fde9c /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Merge TARGET_POWER_ON and PANEL_POWER_ON flag definitions (diff) | |
| download | kernel-qcow2-linux-ed6143b8f7537db98e94feeb50e7b7f698c7cb05.tar.gz kernel-qcow2-linux-ed6143b8f7537db98e94feeb50e7b7f698c7cb05.tar.xz kernel-qcow2-linux-ed6143b8f7537db98e94feeb50e7b7f698c7cb05.zip | |
drm/i915/lvds: Restore initial HW state during encoder enabling
Atm the LVDS encoder depends on the PPS HW context being saved/restored
from generic suspend/resume code. Since the PPS is specific to the LVDS
and eDP encoders a cleaner way is to reinitialize it during encoder
enabling, so do this here for LVDS. Follow-up patches will init the PPS
for the eDP encoder similarly and remove the suspend/resume time save /
restore.
v2:
- Apply BSpec +1 offset and use DIV_ROUND_UP() when programming the
power cycle delay. (Ville)
v3: (Ville)
- Fix +1 vs. round-up order.
- s/reset_on_powerdown/powerdown_on_reset/
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470827254-21954-3-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 889508fdbe98..da82744f3a3b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3710,6 +3710,7 @@ enum { #define _PP_ON_DELAYS 0x61208 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) +#define PANEL_PORT_SELECT_SHIFT 30 #define PANEL_PORT_SELECT_MASK (3 << 30) #define PANEL_PORT_SELECT_LVDS (0 << 30) #define PANEL_PORT_SELECT_DPA (1 << 30) |