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| author | Ville Syrjälä | 2015-07-08 22:45:57 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2015-08-26 14:37:24 +0200 |
| commit | ee27921824e6ad0ca2d8e5abfa12cf4d853ded6c (patch) | |
| tree | 1904356a78eb8ebfbec55dfd589fd7743e296662 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Force common lane on for the PPS kick on CHV (diff) | |
| download | kernel-qcow2-linux-ee27921824e6ad0ca2d8e5abfa12cf4d853ded6c.tar.gz kernel-qcow2-linux-ee27921824e6ad0ca2d8e5abfa12cf4d853ded6c.tar.xz kernel-qcow2-linux-ee27921824e6ad0ca2d8e5abfa12cf4d853ded6c.zip | |
drm/i915: Enable DPIO SUS clock gating on CHV
CHV has supports some form of automagic clock gating for the
DPIO SUS clock. We can simply enable the magic bits and the
hardware should take care of the rest.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6918ffab168e..6ed7141c9505 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1143,6 +1143,10 @@ enum skl_disp_power_wells { #define CHV_CMN_DW28 0x8170 #define DPIO_CL1POWERDOWNEN (1 << 23) #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) +#define DPIO_SUS_CLK_CONFIG_ON (0 << 0) +#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) +#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) +#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) #define CHV_CMN_DW30 0x8178 #define DPIO_LRC_BYPASS (1 << 3) |