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| author | Imre Deak | 2015-09-30 22:00:42 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2015-10-02 09:41:02 +0200 |
| commit | f1d543485344f11f90e5fac637cc3430841ddabf (patch) | |
| tree | 3c002d6698ba1715b3e5679b0c31c913b1a935aa /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset (diff) | |
| download | kernel-qcow2-linux-f1d543485344f11f90e5fac637cc3430841ddabf.tar.gz kernel-qcow2-linux-f1d543485344f11f90e5fac637cc3430841ddabf.tar.xz kernel-qcow2-linux-f1d543485344f11f90e5fac637cc3430841ddabf.zip | |
drm/i915: remove duplicate names for the render ring INSTDONE register
We use 3 different names to refer to the same render ring INSTDONE
register. This can be confusing when comparing two parts of the code
accessing the register via different names. Although the GEN4 version's
layout is different, we treat it the same way as the GEN7+ version, in
that we simply read it out during error capture. So remove the
duplicates and leave a comment about the GEN4 difference.
Note that there is also a GEN2 version of this register, but that's on a
different address so not handled in this patch.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9e3fdb372275..d1e3c3cd27cf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1593,14 +1593,16 @@ enum skl_disp_power_wells { #endif #define IPEIR_I965 0x02064 #define IPEHR_I965 0x02068 -#define INSTDONE_I965 0x0206c -#define GEN7_INSTDONE_1 0x0206c #define GEN7_SC_INSTDONE 0x07100 #define GEN7_SAMPLER_INSTDONE 0x0e160 #define GEN7_ROW_INSTDONE 0x0e164 #define I915_NUM_INSTDONE_REG 4 #define RING_IPEIR(base) ((base)+0x64) #define RING_IPEHR(base) ((base)+0x68) +/* + * On GEN4, only the render ring INSTDONE exists and has a different + * layout than the GEN7+ version. + */ #define RING_INSTDONE(base) ((base)+0x6c) #define RING_INSTPS(base) ((base)+0x70) #define RING_DMA_FADD(base) ((base)+0x78) |