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| author | Ville Syrjälä | 2015-12-04 21:19:39 +0100 |
|---|---|---|
| committer | Ville Syrjälä | 2015-12-08 15:30:20 +0100 |
| commit | f7be2c2150b0457ae88cb1cf7799846f996d72c7 (patch) | |
| tree | 1d63b777ffee130e0e2f72bd6ac24d8039a924a6 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/skl: Double RC6 WRL always on (diff) | |
| download | kernel-qcow2-linux-f7be2c2150b0457ae88cb1cf7799846f996d72c7.tar.gz kernel-qcow2-linux-f7be2c2150b0457ae88cb1cf7799846f996d72c7.tar.xz kernel-qcow2-linux-f7be2c2150b0457ae88cb1cf7799846f996d72c7.zip | |
drm/i915: Disable CLKOUT_DP bending on LPT/WPT as needed
When we want to use SPLL for FDI we want SSC, which means we have to
disable clock bending for the PCH SSC reference (bend and spread are
mutually exclusive). So let's turn off bending when we want spread.
In case the BIOS enabled clock bending for some reason we'll just turn
it off and enable the spread mode instead.
Not sure what happens if the BIOS is actually using the bend source for
HDMI at this time, but I suppose it should be no worse than what already
happens when we simply turn on the spread.
We don't currently use the bend source for anything, and only use the
PCH SSC reference for the SPLL to drive FDI (always with spread).
v2: Fix the %5 vs %10 fumble for SSCDITHPHASE (Paulo)
Add 'WARN_ON(steps % 5 != 0)' sanity check (Paulo)
Fix typos in commit message (Paulo)
Cc: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1449260379-14093-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 206b213a74e1..ef16c4236d9f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7327,6 +7327,7 @@ enum skl_disp_power_wells { #define SBI_READY (0x0<<0) /* SBI offsets */ +#define SBI_SSCDIVINTPHASE 0x0200 #define SBI_SSCDIVINTPHASE6 0x0600 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) @@ -7334,6 +7335,7 @@ enum skl_disp_power_wells { #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) +#define SBI_SSCDITHPHASE 0x0204 #define SBI_SSCCTL 0x020c #define SBI_SSCCTL6 0x060C #define SBI_SSCCTL_PATHALT (1<<3) |