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author | Imre Deak | 2018-11-01 15:04:27 +0100 |
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committer | Imre Deak | 2018-11-02 00:24:04 +0100 |
commit | 70332ac539c5c5dffede580fe8986dcfc0751d55 (patch) | |
tree | 6b93c6b1cafff107835758025fa1e3c45ae3684b /drivers/gpu/drm/i915/intel_ddi.c | |
parent | drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain (diff) | |
download | kernel-qcow2-linux-70332ac539c5c5dffede580fe8986dcfc0751d55.tar.gz kernel-qcow2-linux-70332ac539c5c5dffede580fe8986dcfc0751d55.tar.xz kernel-qcow2-linux-70332ac539c5c5dffede580fe8986dcfc0751d55.zip |
drm/i915/icl+: Sanitize port to PLL mapping
BIOS can leave the PLL to port mapping enabled, even if the
corresponding encoder is disabled. Disable the port mapping in this
case.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-9-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 40dfa0793c95..3eea987e909b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2822,6 +2822,29 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc, } } +void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + u32 val = I915_READ(DPCLKA_CFGCR0_ICL); + enum port port = encoder->port; + bool clk_enabled = !(val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)); + + if (clk_enabled == !!encoder->base.crtc) + return; + + /* + * Punt on the case now where clock is disabled, but the encoder is + * enabled, something else is really broken then. + */ + if (WARN_ON(!clk_enabled)) + return; + + DRM_NOTE("Port %c is disabled but it has a mapped PLL, unmap it\n", + port_name(port)); + val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port); + I915_WRITE(DPCLKA_CFGCR0_ICL, val); +} + static void intel_ddi_clk_select(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { |