diff options
| author | Paulo Zanoni | 2018-07-25 02:28:13 +0200 |
|---|---|---|
| committer | Paulo Zanoni | 2018-07-25 22:45:26 +0200 |
| commit | bc334d914eeee02eddefd7be533acafd9a042ade (patch) | |
| tree | 7c97e1333ee1caed6129c34c9ebb2d935fac9e4c /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | drm/i915/icl: program MG_DP_MODE (diff) | |
| download | kernel-qcow2-linux-bc334d914eeee02eddefd7be533acafd9a042ade.tar.gz kernel-qcow2-linux-bc334d914eeee02eddefd7be533acafd9a042ade.tar.xz kernel-qcow2-linux-bc334d914eeee02eddefd7be533acafd9a042ade.zip | |
drm/i915/icl: toggle PHY clock gating around link training
The Gen11 TypeC PHY DDI Buffer chapter, PHY Clock Gating Programming
section says that PHY clock gating should be disabled before starting
voltage swing programming, then enabled after any link training is
complete.
v2: Simple rebase.
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180725002813.6938-6-paulo.r.zanoni@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 399c438bd210..0adc043529f2 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2810,6 +2810,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); icl_program_mg_dp_mode(intel_dp); + icl_disable_phy_clock_gating(dig_port); if (IS_ICELAKE(dev_priv)) icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, @@ -2828,6 +2829,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) intel_dp_stop_link_train(intel_dp); + icl_enable_phy_clock_gating(dig_port); + intel_ddi_enable_pipe_clock(crtc_state); } |