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| author | Rodrigo Vivi | 2014-08-01 11:04:45 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-08-08 17:43:46 +0200 |
| commit | da46f936bb0396f6a0fb87c2786f541e9f19a73c (patch) | |
| tree | 660b167fef796a2b60678443078a2039b9e91159 /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | drm/i915: Align intel_dsi*.c files a bit (diff) | |
| download | kernel-qcow2-linux-da46f936bb0396f6a0fb87c2786f541e9f19a73c.tar.gz kernel-qcow2-linux-da46f936bb0396f6a0fb87c2786f541e9f19a73c.tar.xz kernel-qcow2-linux-da46f936bb0396f6a0fb87c2786f541e9f19a73c.zip | |
drm/i915: Introduce FBC False Color for debug purposes.
With this bit enabled, HW changes the color when compressing frames for
debug purposes.
ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the workload
it is not possible to set this bit with intel-gpu-tools. So this patch
introduces a persistent way to enable false color over debugfs.
v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
v3: (Ville) only do false color for IVB+ since according to spec bit is
MBZ before IVB.
v4: We don't have FBC on valleyview nor on cherryview (Ben)
v5: s/!HAS_PCH_SPLIT/!HAS_FBC (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
0 files changed, 0 insertions, 0 deletions