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authorPaulo Zanoni2012-08-08 19:15:29 +0200
committerDaniel Vetter2012-08-09 18:41:14 +0200
commitdfcef252e024b4ca6fe5be9e1d656ac1929ce894 (patch)
treeb37f47268987b7c3e5f10391cee44b1a812b046f /drivers/gpu/drm/i915/intel_ddi.c
parentdrm/i915: set the DDI sync polarity bits (diff)
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drm/i915: correctly set the DDI_FUNC_CTL bpc field
Correctly erase the values previously set and also check for 6bpc and 10bpc. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c26
1 files changed, 20 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1fbd67cd5586..8b383593b0d3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -725,14 +725,28 @@ void intel_ddi_mode_set(struct drm_encoder *encoder,
/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = I915_READ(DDI_FUNC_CTL(pipe));
temp &= ~PIPE_DDI_PORT_MASK;
- temp &= ~PIPE_DDI_BPC_12;
+ temp &= ~PIPE_DDI_BPC_MASK;
temp &= ~PIPE_DDI_MODE_SELECT_MASK;
temp &= ~(PIPE_DDI_PVSYNC | PIPE_DDI_PHSYNC);
- temp |= PIPE_DDI_SELECT_PORT(port) |
- ((intel_crtc->bpp > 24) ?
- PIPE_DDI_BPC_12 :
- PIPE_DDI_BPC_8) |
- PIPE_DDI_FUNC_ENABLE;
+ temp |= PIPE_DDI_FUNC_ENABLE | PIPE_DDI_SELECT_PORT(port);
+
+ switch (intel_crtc->bpp) {
+ case 18:
+ temp |= PIPE_DDI_BPC_6;
+ break;
+ case 24:
+ temp |= PIPE_DDI_BPC_8;
+ break;
+ case 30:
+ temp |= PIPE_DDI_BPC_10;
+ break;
+ case 36:
+ temp |= PIPE_DDI_BPC_12;
+ break;
+ default:
+ WARN(1, "%d bpp unsupported by pipe DDI function\n",
+ intel_crtc->bpp);
+ }
if (intel_hdmi->has_hdmi_sink)
temp |= PIPE_DDI_MODE_SELECT_HDMI;