diff options
| author | Rodrigo Vivi | 2018-10-22 19:15:22 +0200 |
|---|---|---|
| committer | Rodrigo Vivi | 2018-10-22 23:40:35 +0200 |
| commit | fdec4df43ca5171a05e7cfec7e89efb295ff87e5 (patch) | |
| tree | f7c1138466c7fa153fcc0fdfbc1409ccafdccda3 /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | drm/i915/icl: Define DSI panel programming registers (diff) | |
| download | kernel-qcow2-linux-fdec4df43ca5171a05e7cfec7e89efb295ff87e5.tar.gz kernel-qcow2-linux-fdec4df43ca5171a05e7cfec7e89efb295ff87e5.tar.xz kernel-qcow2-linux-fdec4df43ca5171a05e7cfec7e89efb295ff87e5.zip | |
drm/i915: ddi_clock_get sort platforms newer-to-older.
No functional change.
Just sorting this "if" block from newer to older platform.
v2: Invert gen9_bc and gen9_lp (Ville)
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181022171526.15641-1-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 6b9742baa5f2..e4f8e738c47b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1737,16 +1737,16 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - if (INTEL_GEN(dev_priv) <= 8) - hsw_ddi_clock_get(encoder, pipe_config); - else if (IS_GEN9_BC(dev_priv)) - skl_ddi_clock_get(encoder, pipe_config); - else if (IS_GEN9_LP(dev_priv)) - bxt_ddi_clock_get(encoder, pipe_config); + if (IS_ICELAKE(dev_priv)) + icl_ddi_clock_get(encoder, pipe_config); else if (IS_CANNONLAKE(dev_priv)) cnl_ddi_clock_get(encoder, pipe_config); - else if (IS_ICELAKE(dev_priv)) - icl_ddi_clock_get(encoder, pipe_config); + else if (IS_GEN9_LP(dev_priv)) + bxt_ddi_clock_get(encoder, pipe_config); + else if (IS_GEN9_BC(dev_priv)) + skl_ddi_clock_get(encoder, pipe_config); + else if (INTEL_GEN(dev_priv) <= 8) + hsw_ddi_clock_get(encoder, pipe_config); } void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state) |