diff options
| author | Ville Syrjälä | 2016-05-13 22:41:34 +0200 |
|---|---|---|
| committer | Ville Syrjälä | 2016-05-23 20:11:15 +0200 |
| commit | 2b73001e739d3db8474472b7e6585ef9ee4b946e (patch) | |
| tree | b663bd2cc0385c4d92af279e366eaac0df83dfb0 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Store cdclk PLL reference clock under dev_priv (diff) | |
| download | kernel-qcow2-linux-2b73001e739d3db8474472b7e6585ef9ee4b946e.tar.gz kernel-qcow2-linux-2b73001e739d3db8474472b7e6585ef9ee4b946e.tar.xz kernel-qcow2-linux-2b73001e739d3db8474472b7e6585ef9ee4b946e.zip | |
drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()
Enabling and disalbing the DE PLL are two nice self contained
operations, so let's move them into a few small helper functions.
Makes it easier to see the forest from the trees in broxton_set_cdclk().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-16-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 41 |
1 files changed, 27 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 57771639b94e..521ad133deb8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5278,6 +5278,31 @@ static int skl_cdclk_decimal(int cdclk) return DIV_ROUND_CLOSEST(cdclk - 1000, 500); } +static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) +{ + I915_WRITE(BXT_DE_PLL_ENABLE, 0); + + /* Timeout 200us */ + if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) + DRM_ERROR("timeout waiting for DE PLL unlock\n"); +} + +static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio) +{ + u32 val; + + val = I915_READ(BXT_DE_PLL_CTL); + val &= ~BXT_DE_PLL_RATIO_MASK; + val |= ratio; + I915_WRITE(BXT_DE_PLL_CTL, val); + + I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); + + /* Timeout 200us */ + if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) + DRM_ERROR("timeout waiting for DE PLL lock\n"); +} + static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) { uint32_t divider; @@ -5345,25 +5370,13 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) */ if (cdclk == 19200 || cdclk == 624000 || current_cdclk == 624000) { - I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); - /* Timeout 200us */ - if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), - 1)) - DRM_ERROR("timout waiting for DE PLL unlock\n"); + bxt_de_pll_disable(dev_priv); } if (cdclk != 19200) { uint32_t val; - val = I915_READ(BXT_DE_PLL_CTL); - val &= ~BXT_DE_PLL_RATIO_MASK; - val |= ratio; - I915_WRITE(BXT_DE_PLL_CTL, val); - - I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); - /* Timeout 200us */ - if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) - DRM_ERROR("timeout waiting for DE PLL lock\n"); + bxt_de_pll_enable(dev_priv, ratio); val = divider | skl_cdclk_decimal(cdclk); /* |