diff options
| author | Ville Syrjälä | 2016-11-18 20:52:57 +0100 |
|---|---|---|
| committer | Ville Syrjälä | 2016-12-15 13:55:30 +0100 |
| commit | 2f3f4763c1ba9348984ed67aa60a16c86a9dab1c (patch) | |
| tree | 72a152ffc765eda91f400b9b85ccb2b7d0ef38e3 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm: Store a pointer to drm_format_info under drm_framebuffer (diff) | |
| download | kernel-qcow2-linux-2f3f4763c1ba9348984ed67aa60a16c86a9dab1c.tar.gz kernel-qcow2-linux-2f3f4763c1ba9348984ed67aa60a16c86a9dab1c.tar.xz kernel-qcow2-linux-2f3f4763c1ba9348984ed67aa60a16c86a9dab1c.zip | |
drm/i915: Populate fb->format early for inherited fbs
Make sure the framebuffer format info is available as early as possible
for fbs we inherit from the BIOS. This will allow us to use the fb as
if it was fully formed before we register it.
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1479498793-31021-22-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 030adf255afe..a760814ec974 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8717,6 +8717,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fourcc = i9xx_format_to_fourcc(pixel_format); fb->pixel_format = fourcc; fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; + fb->format = drm_format_info(fourcc); if (INTEL_GEN(dev_priv) >= 4) { if (plane_config->tiling) @@ -9748,6 +9749,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, val & PLANE_CTL_ALPHA_MASK); fb->pixel_format = fourcc; fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; + fb->format = drm_format_info(fourcc); tiling = val & PLANE_CTL_TILED_MASK; switch (tiling) { @@ -9863,6 +9865,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc, fourcc = i9xx_format_to_fourcc(pixel_format); fb->pixel_format = fourcc; fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; + fb->format = drm_format_info(fourcc); base = I915_READ(DSPSURF(pipe)) & 0xfffff000; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |