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| author | Chris Wilson | 2010-12-05 17:45:02 +0100 |
|---|---|---|
| committer | Chris Wilson | 2010-12-06 00:18:31 +0100 |
| commit | 3c8cdf9b60b98c5b408e2cfbcab3160e25e5af5a (patch) | |
| tree | fd67f13bcf05f42f2162db7b4b54bdf817e9eebc /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Avoid using PIPE_CONTROL on Ironlake (diff) | |
| download | kernel-qcow2-linux-3c8cdf9b60b98c5b408e2cfbcab3160e25e5af5a.tar.gz kernel-qcow2-linux-3c8cdf9b60b98c5b408e2cfbcab3160e25e5af5a.tar.xz kernel-qcow2-linux-3c8cdf9b60b98c5b408e2cfbcab3160e25e5af5a.zip | |
drm/i915: Power Context register is only available for gen4 mobiles
The ability to save the hardware context upon powering down the render
clock through PWRCTXA is only available on a couple of gen4 chipsets.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a95c69392afc..aba1c33f6407 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5973,7 +5973,7 @@ void intel_init_clock_gating(struct drm_device *dev) "Disable RC6\n"); } - if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { + if (IS_GEN4(dev) && IS_MOBILE(dev)) { if (dev_priv->pwrctx == NULL) dev_priv->pwrctx = intel_alloc_context_page(dev); if (dev_priv->pwrctx) { |