diff options
| author | Zhao Yakui | 2009-11-20 04:24:18 +0100 |
|---|---|---|
| committer | Eric Anholt | 2009-11-25 22:03:12 +0100 |
| commit | 4215866059b126590aceddfe9f846595b0c1f458 (patch) | |
| tree | b942b729718c4b3e40033c02ba20ba8e3cc14212 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Check whether the LVDS downclock is found in VBT (diff) | |
| download | kernel-qcow2-linux-4215866059b126590aceddfe9f846595b0c1f458.tar.gz kernel-qcow2-linux-4215866059b126590aceddfe9f846595b0c1f458.tar.xz kernel-qcow2-linux-4215866059b126590aceddfe9f846595b0c1f458.zip | |
drm/i915: Restore the DPLL calculation logic for 9xx platform
The DPLL calculation logic for 9xx platform is changed in:
commit 652c393a3368af84359da37c45afc35a91144960
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Mon Aug 17 13:31:43 2009 -0700
drm/i915: add dynamic clock frequency control
Maybe we will get the different M/N/P combination with that by using the
previous dpll calculation logic.
So restore the DPLL calculation logic for 9xx platform.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a65838ed24b9..e25601bbcb57 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -706,16 +706,17 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, memset (best_clock, 0, sizeof (*best_clock)); - for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { - for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; - clock.m1++) { - for (clock.m2 = limit->m2.min; - clock.m2 <= limit->m2.max; clock.m2++) { - /* m1 is always 0 in IGD */ - if (clock.m2 >= clock.m1 && !IS_IGD(dev)) - break; - for (clock.n = limit->n.min; - clock.n <= limit->n.max; clock.n++) { + for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; + clock.m1++) { + for (clock.m2 = limit->m2.min; + clock.m2 <= limit->m2.max; clock.m2++) { + /* m1 is always 0 in IGD */ + if (clock.m2 >= clock.m1 && !IS_IGD(dev)) + break; + for (clock.n = limit->n.min; + clock.n <= limit->n.max; clock.n++) { + for (clock.p1 = limit->p1.min; + clock.p1 <= limit->p1.max; clock.p1++) { int this_err; intel_clock(dev, refclk, &clock); |