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| author | Ander Conselvan de Oliveira | 2015-04-21 16:13:21 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2015-05-08 13:04:09 +0200 |
| commit | 4978cc93d9ac240b435ce60431aef24239b4c270 (patch) | |
| tree | 8d48e9a36fb0197593d84a21ad6250682ac4ab92 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Take ownership of atomic state on success in intel_set_mode() (diff) | |
| download | kernel-qcow2-linux-4978cc93d9ac240b435ce60431aef24239b4c270.tar.gz kernel-qcow2-linux-4978cc93d9ac240b435ce60431aef24239b4c270.tar.xz kernel-qcow2-linux-4978cc93d9ac240b435ce60431aef24239b4c270.zip | |
drm/i915: Preserve shared DPLL information in new pipe_config
When a new pipe_config is calculated, the fields related to shared dplls
are reset, under the assumption that they will be recalculated as part
of the modeset, which is true with the current state of the code.
As we convert to atomic, however, it will be possible to calculate a new
pipe_config and skip the modeset. In that case, after the state swap we
still want the shared dplls to be preserved.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e3e4a04a18bf..b392ce3dd6c1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11467,13 +11467,21 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) { struct drm_crtc_state tmp_state; struct intel_crtc_scaler_state scaler_state; + struct intel_dpll_hw_state dpll_hw_state; + enum intel_dpll_id shared_dpll; /* Clear only the intel specific part of the crtc state excluding scalers */ tmp_state = crtc_state->base; scaler_state = crtc_state->scaler_state; + shared_dpll = crtc_state->shared_dpll; + dpll_hw_state = crtc_state->dpll_hw_state; + memset(crtc_state, 0, sizeof *crtc_state); + crtc_state->base = tmp_state; crtc_state->scaler_state = scaler_state; + crtc_state->shared_dpll = shared_dpll; + crtc_state->dpll_hw_state = dpll_hw_state; } static int @@ -11502,7 +11510,6 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, pipe_config->cpu_transcoder = (enum transcoder) to_intel_crtc(crtc)->pipe; - pipe_config->shared_dpll = DPLL_ID_PRIVATE; /* * Sanitize sync polarity flags based on requested ones. If neither @@ -12266,9 +12273,14 @@ static int __intel_set_mode_setup_plls(struct drm_atomic_state *state) for_each_crtc_in_state(state, crtc, crtc_state, i) { intel_crtc = to_intel_crtc(crtc); + intel_crtc_state = to_intel_crtc_state(crtc_state); - if (needs_modeset(crtc_state)) + if (needs_modeset(crtc_state)) { clear_pipes |= 1 << intel_crtc->pipe; + intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; + memset(&intel_crtc_state->dpll_hw_state, 0, + sizeof(intel_crtc_state->dpll_hw_state)); + } } ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); |