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| author | Imre Deak | 2014-06-25 21:01:49 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-07-10 22:04:53 +0200 |
| commit | 4fe9467d216af71fb456d626ee26e17178d619f9 (patch) | |
| tree | 92fdd3bd4f000eb15fed451568e556ec02da8f0d /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Clean up WRPLL/SPLL #defines (diff) | |
| download | kernel-qcow2-linux-4fe9467d216af71fb456d626ee26e17178d619f9.tar.gz kernel-qcow2-linux-4fe9467d216af71fb456d626ee26e17178d619f9.tar.xz kernel-qcow2-linux-4fe9467d216af71fb456d626ee26e17178d619f9.zip | |
drm/i915: ddi: move pch setup after encoder->pre_enable
This is needed by an upcoming patch that moves the PCH/CRT PLL enabling
into the pre_enable hook, after which we want to keep the modeset
sequence at its current state. At this point this won't have an effect
since the PCH/CRT pre_enable hook is atm a NOP.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e1b0049347a6..8ce89c8aa92b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4100,16 +4100,15 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_crtc->active = true; intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); - if (intel_crtc->config.has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); - - if (intel_crtc->config.has_pch_encoder) - dev_priv->display.fdi_link_train(crtc); - for_each_encoder_on_crtc(dev, crtc, encoder) if (encoder->pre_enable) encoder->pre_enable(encoder); + if (intel_crtc->config.has_pch_encoder) { + intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); + dev_priv->display.fdi_link_train(crtc); + } + intel_ddi_enable_pipe_clock(intel_crtc); ironlake_pfit_enable(intel_crtc); |