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| author | Paulo Zanoni | 2013-01-29 19:35:19 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2013-01-31 11:50:11 +0100 |
| commit | 693101618a4beedf1b3d291860aee56c5fe44a1c (patch) | |
| tree | 57e90a357db1ffe55b7b18f5f652b7f622cfd406 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: don't send DP "idle" pattern before "normal" on HSW PORT_A (diff) | |
| download | kernel-qcow2-linux-693101618a4beedf1b3d291860aee56c5fe44a1c.tar.gz kernel-qcow2-linux-693101618a4beedf1b3d291860aee56c5fe44a1c.tar.xz kernel-qcow2-linux-693101618a4beedf1b3d291860aee56c5fe44a1c.zip | |
drm/i915: check the power down well on assert_pipe()
If the power well is disabled, we should not try to read its
registers, otherwise we'll get "unclaimed register" messages.
V2: Don't check whether the power well is enabled or not, just check
whether we asked it to be enabled or not: if we asked to disable the
power well, don't use the registers on it, even if it's still enabled.
V3: Fix bug that breaks all non-Haswell machines.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0d45487040d2..429b66bcb5b2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1214,9 +1214,15 @@ void assert_pipe(struct drm_i915_private *dev_priv, if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) state = true; - reg = PIPECONF(cpu_transcoder); - val = I915_READ(reg); - cur_state = !!(val & PIPECONF_ENABLE); + if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP && + !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) { + cur_state = false; + } else { + reg = PIPECONF(cpu_transcoder); + val = I915_READ(reg); + cur_state = !!(val & PIPECONF_ENABLE); + } + WARN(cur_state != state, "pipe %c assertion failure (expected %s, current %s)\n", pipe_name(pipe), state_string(state), state_string(cur_state)); |