diff options
| author | Ville Syrjälä | 2015-10-07 21:08:24 +0200 |
|---|---|---|
| committer | Jani Nikula | 2015-10-13 16:03:18 +0200 |
| commit | 8e7a65aa70bcc1235a44e40ae0da5056525fe081 (patch) | |
| tree | df12be3c597c742f5e3fff3419a78c78e2e1cd07 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Flush pipecontrol post-sync writes (diff) | |
| download | kernel-qcow2-linux-8e7a65aa70bcc1235a44e40ae0da5056525fe081.tar.gz kernel-qcow2-linux-8e7a65aa70bcc1235a44e40ae0da5056525fe081.tar.xz kernel-qcow2-linux-8e7a65aa70bcc1235a44e40ae0da5056525fe081.zip | |
drm/i915: Restore lost DPLL register write on gen2-4
We accidentally lost the initial DPLL register write in
1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
The "three times for luck" hack probably saved us from a total
disaster. But anyway, bring the initial write back so that the
code actually makes some sense.
Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca>
References: http://mid.gmane.org/CAN_QmVyMaArxYgEcVVsGvsMo7-6ohZr8HmF5VhkkL4i9KOmrhw@mail.gmail.com
Cc: stable@vger.kernel.org
Cc: Nick Bowler <nbowler@draconx.ca>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cf418be7d30a..bdfac53dd945 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1724,6 +1724,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); } + I915_WRITE(reg, dpll); + /* Wait for the clocks to stabilize. */ POSTING_READ(reg); udelay(150); |