diff options
| author | Ville Syrjälä | 2015-10-29 20:25:51 +0100 |
|---|---|---|
| committer | Ville Syrjälä | 2015-11-10 15:22:53 +0100 |
| commit | 9c4edaeea08896dbcc3925810963ec8ddd1ccfc4 (patch) | |
| tree | 6ce2ffb362bc6efc1f5cd28fb9035f05015adea6 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config... (diff) | |
| download | kernel-qcow2-linux-9c4edaeea08896dbcc3925810963ec8ddd1ccfc4.tar.gz kernel-qcow2-linux-9c4edaeea08896dbcc3925810963ec8ddd1ccfc4.tar.xz kernel-qcow2-linux-9c4edaeea08896dbcc3925810963ec8ddd1ccfc4.zip | |
drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL
Rather than looking at crtc->mode (which is the user mode) dig up the
sync polarity settings from the adjusted_mode when programming
TRANS_DP_CTL on CPT/PPT.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446146763-31821-3-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f42d5d872fee..a2d5938a9367 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4139,6 +4139,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) /* For PCH DP, enable TRANS_DP_CTL */ if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { + const struct drm_display_mode *adjusted_mode = + &intel_crtc->config->base.adjusted_mode; u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; reg = TRANS_DP_CTL(pipe); temp = I915_READ(reg); @@ -4148,9 +4150,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) temp |= TRANS_DP_OUTPUT_ENABLE; temp |= bpc << 9; /* same format but at 11:9 */ - if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) + if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; - if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) + if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; switch (intel_trans_dp_port_sel(crtc)) { |