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| author | Keith Packard | 2011-09-27 05:42:37 +0200 |
|---|---|---|
| committer | Keith Packard | 2011-09-28 23:08:37 +0200 |
| commit | afffb9dfb62a9eb2a6e467a3875907189e49a2d2 (patch) | |
| tree | 28e3a7623278c050340c26554af13941f086b683 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Use CK505 as non-SSC source where available (diff) | |
| download | kernel-qcow2-linux-afffb9dfb62a9eb2a6e467a3875907189e49a2d2.tar.gz kernel-qcow2-linux-afffb9dfb62a9eb2a6e467a3875907189e49a2d2.tar.xz kernel-qcow2-linux-afffb9dfb62a9eb2a6e467a3875907189e49a2d2.zip | |
drm/i915: All PCH refclks are 120MHz
I can't find any reference clocks which run at 96MHz as seems to be
indicated from the comments in this code.
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4c9684c54f18..b072a35b6f52 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5281,16 +5281,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, num_connectors++; } - if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { - refclk = dev_priv->lvds_ssc_freq * 1000; - DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", - refclk / 1000); - } else { - refclk = 96000; - if (!has_edp_encoder || - intel_encoder_is_pch_edp(&has_edp_encoder->base)) - refclk = 120000; /* 120Mhz refclk */ - } + /* + * Every reference clock in a PCH system is 120MHz + */ + refclk = 120000; /* * Returns a set of divisors for the desired target clock with the given |