diff options
| author | Daniel Vetter | 2012-10-26 10:58:13 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2012-11-11 23:50:57 +0100 |
| commit | d74cf324e2b64349a49d0f17e9f6764f8a7d8349 (patch) | |
| tree | 8fba7fd2b0d72d98629b6f1f2421f31b7f22a0a3 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: clarify why we need to enable fdi plls so early (diff) | |
| download | kernel-qcow2-linux-d74cf324e2b64349a49d0f17e9f6764f8a7d8349.tar.gz kernel-qcow2-linux-d74cf324e2b64349a49d0f17e9f6764f8a7d8349.tar.xz kernel-qcow2-linux-d74cf324e2b64349a49d0f17e9f6764f8a7d8349.zip | |
drm/i915: set FDI_RX_MISC to recommended values on CPT/PPT
My machine here has the correct ones already, but better safe
than sorry. IBX has different settings for that register, and
on IBX the device defaults match the recommended values. Hence
I did not add the respective writes for IBX.
LPT needs the same settings, but that has been done already
commit 4acf518626cdad5bbf7aac9869bd4accbbfb4ad3
Author: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date: Wed Jul 4 20:15:16 2012 -0300
drm/i915: program FDI_RX TP and FDI delays
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 612b4105b758..a3e715b4290d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2479,6 +2479,9 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc) temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; I915_WRITE(reg, temp | FDI_TX_ENABLE); + I915_WRITE(FDI_RX_MISC(pipe), + FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); + reg = FDI_RX_CTL(pipe); temp = I915_READ(reg); if (HAS_PCH_CPT(dev)) { @@ -2611,6 +2614,9 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) temp |= FDI_COMPOSITE_SYNC; I915_WRITE(reg, temp | FDI_TX_ENABLE); + I915_WRITE(FDI_RX_MISC(pipe), + FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); + reg = FDI_RX_CTL(pipe); temp = I915_READ(reg); temp &= ~FDI_LINK_TRAIN_AUTO; |