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| author | Ville Syrjälä | 2013-06-07 09:47:01 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2013-06-07 10:37:48 +0200 |
| commit | de1aa629aac8377bdfc55674bb8e30b5f15f418d (patch) | |
| tree | 241af500146460fda42980b4c8b3807f75ccfa18 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: enable 30bpp for DP outputs (diff) | |
| download | kernel-qcow2-linux-de1aa629aac8377bdfc55674bb8e30b5f15f418d.tar.gz kernel-qcow2-linux-de1aa629aac8377bdfc55674bb8e30b5f15f418d.tar.xz kernel-qcow2-linux-de1aa629aac8377bdfc55674bb8e30b5f15f418d.zip | |
drm/i915: Disable primary plane trickle feed for g4x
The docs say that the trickle feed disable bit is present (for primary
planes only, not video sprites) on CTG, and that it must be set
for ELK. Just set it for all g4x chipsets.
v2: Do it in init_clock_gating too
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8d9e7c0e9e4b..3f025ee299dd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1958,6 +1958,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, dspcntr &= ~DISPPLANE_TILED; } + if (IS_G4X(dev)) + dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; + I915_WRITE(reg, dspcntr); linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |