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| author | Vijay Purushothaman | 2015-03-05 15:02:06 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2015-03-17 22:30:13 +0100 |
| commit | de3a0fde9afe551440db486f3f5ee52c8f15120a (patch) | |
| tree | 4e8ea2c191542137e8880a723e6c0b2ff66510ee /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Disable M2 frac division for integer case (diff) | |
| download | kernel-qcow2-linux-de3a0fde9afe551440db486f3f5ee52c8f15120a.tar.gz kernel-qcow2-linux-de3a0fde9afe551440db486f3f5ee52c8f15120a.tar.xz kernel-qcow2-linux-de3a0fde9afe551440db486f3f5ee52c8f15120a.zip | |
drm/i915: Initialize CHV digital lock detect threshold
Initialize lock detect threshold and select coarse threshold for the
case where M2 fraction division is disabled.
v2: Split the changes into multiple smaller patches (Ville)
v3: Clear out the old bits before we modify those bits as RMW (Ville)
v4: Reset coarse threshold when M2 fraction is enabled (Ville)
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8676cb8deaf8..2eea258e5865 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6207,6 +6207,15 @@ static void chv_prepare_pll(struct intel_crtc *crtc, dpio_val |= DPIO_CHV_FRAC_DIV_EN; vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); + /* Program digital lock detect threshold */ + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); + dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | + DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); + dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); + if (!bestm2_frac) + dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); + /* Loop filter */ refclk = i9xx_get_refclk(crtc, 0); loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | |