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| author | Tvrtko Ursulin | 2015-03-23 12:10:35 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2015-03-23 15:01:44 +0100 |
| commit | f64b98cd2e40052c17f67f09a081ff292bac0f77 (patch) | |
| tree | 2163e7c62ae8fba8a8ffe038d322056563680b0c /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Pass in plane state when (un)pinning frame buffers (diff) | |
| download | kernel-qcow2-linux-f64b98cd2e40052c17f67f09a081ff292bac0f77.tar.gz kernel-qcow2-linux-f64b98cd2e40052c17f67f09a081ff292bac0f77.tar.xz kernel-qcow2-linux-f64b98cd2e40052c17f67f09a081ff292bac0f77.zip | |
drm/i915: Helper function to determine GGTT view from plane state
For now only default implementation defaulting to normal view.
v2: Some code review cleanups. (Joonas Lahtinen)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4d8a397893d1..d3fa09bd3e07 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2288,6 +2288,15 @@ intel_fb_align_height(struct drm_device *dev, unsigned int height, fb_format_modifier)); } +static int +intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, + const struct drm_plane_state *plane_state) +{ + *view = i915_ggtt_view_normal; + + return 0; +} + int intel_pin_and_fence_fb_obj(struct drm_plane *plane, struct drm_framebuffer *fb, @@ -2297,6 +2306,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, struct drm_device *dev = fb->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj = intel_fb_obj(fb); + struct i915_ggtt_view view; u32 alignment; int ret; @@ -2333,6 +2343,10 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, return -EINVAL; } + ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); + if (ret) + return ret; + /* Note that the w/a also requires 64 PTE of padding following the * bo. We currently fill all unused PTE with the shadow page and so * we should always have valid PTE following the scanout preventing @@ -2352,7 +2366,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, dev_priv->mm.interruptible = false; ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, - &i915_ggtt_view_normal); + &view); if (ret) goto err_interruptible; @@ -2372,7 +2386,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, return 0; err_unpin: - i915_gem_object_unpin_from_display_plane(obj, &i915_ggtt_view_normal); + i915_gem_object_unpin_from_display_plane(obj, &view); err_interruptible: dev_priv->mm.interruptible = true; intel_runtime_pm_put(dev_priv); @@ -2383,11 +2397,16 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb, const struct drm_plane_state *plane_state) { struct drm_i915_gem_object *obj = intel_fb_obj(fb); + struct i915_ggtt_view view; + int ret; WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); + ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); + WARN_ONCE(ret, "Couldn't get view from plane state!"); + i915_gem_object_unpin_fence(obj); - i915_gem_object_unpin_from_display_plane(obj, &i915_ggtt_view_normal); + i915_gem_object_unpin_from_display_plane(obj, &view); } /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |