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| author | Jesse Barnes | 2015-01-22 02:19:54 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2015-04-16 11:29:06 +0200 |
| commit | ff6d9f55fe3f217dabce6b5ee7dbd306be5f4391 (patch) | |
| tree | ba6a6aad5b9f7ed1dae2397657e5e4adde283e5e /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9 (diff) | |
| download | kernel-qcow2-linux-ff6d9f55fe3f217dabce6b5ee7dbd306be5f4391.tar.gz kernel-qcow2-linux-ff6d9f55fe3f217dabce6b5ee7dbd306be5f4391.tar.xz kernel-qcow2-linux-ff6d9f55fe3f217dabce6b5ee7dbd306be5f4391.zip | |
drm/i915/bxt: fix panel fitter setup in crtc disable/enable
Broxton has the same panel fitter registers as Skylake.
v2:
- add MISSING_CASE for future platforms (daniel)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 783d6008fded..3322e5a12e8e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4881,10 +4881,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_ddi_enable_pipe_clock(intel_crtc); - if (IS_SKYLAKE(dev)) + if (INTEL_INFO(dev)->gen == 9) skylake_pfit_update(intel_crtc, 1); - else + else if (INTEL_INFO(dev)->gen < 9) ironlake_pfit_enable(intel_crtc); + else + MISSING_CASE(INTEL_INFO(dev)->gen); /* * On ILK+ LUT must be loaded before the pipe is running but with @@ -5029,10 +5031,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); - if (IS_SKYLAKE(dev)) + if (INTEL_INFO(dev)->gen == 9) skylake_pfit_update(intel_crtc, 0); - else + else if (INTEL_INFO(dev)->gen < 9) ironlake_pfit_disable(intel_crtc); + else + MISSING_CASE(INTEL_INFO(dev)->gen); intel_ddi_disable_pipe_clock(intel_crtc); @@ -9191,10 +9195,13 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { - if (IS_SKYLAKE(dev)) + if (INTEL_INFO(dev)->gen == 9) skylake_get_pfit_config(crtc, pipe_config); - else + else if (INTEL_INFO(dev)->gen < 9) ironlake_get_pfit_config(crtc, pipe_config); + else + MISSING_CASE(INTEL_INFO(dev)->gen); + } else { pipe_config->scaler_state.scaler_id = -1; pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); |