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| author | Rodrigo Vivi | 2014-09-25 00:16:58 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-09-29 14:21:49 +0200 |
| commit | 8d7f4fe9f561f4e3253478332192d88f6f135c41 (patch) | |
| tree | c9ff9989c8d274cded0ad80e806f4ea46923343d /drivers/gpu/drm/i915/intel_dp.c | |
| parent | drm/i915: Minimize the huge amount of unecessary fbc sw cache clean. (diff) | |
| download | kernel-qcow2-linux-8d7f4fe9f561f4e3253478332192d88f6f135c41.tar.gz kernel-qcow2-linux-8d7f4fe9f561f4e3253478332192d88f6f135c41.tar.xz kernel-qcow2-linux-8d7f4fe9f561f4e3253478332192d88f6f135c41.zip | |
drm/i915: Make sure PSR is ready for been re-enabled.
Let's make sure PSR is propperly disabled before to re-enabled it.
According to Spec, after disabled PSR CTL, the Idle state might occur
up to 24ms, that is one full frame time (1/refresh rate),
plus SRD exit training time (max of 6ms),
plus SRD aux channel handshake (max of 1.5ms).
So if something went wrong PSR will be disabled until next full
enable/disable setup.
v2: The 24ms above takes in account 16ms for refresh rate on 60Hz mode. However
on low frequency modes this can take longer. So let's use 50ms for safeness.
v3: Move wait out of psr.lock critical area.
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c5ec821fa5fb..6f42d9568049 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2204,6 +2204,17 @@ static void intel_edp_psr_work(struct work_struct *work) container_of(work, typeof(*dev_priv), psr.work.work); struct intel_dp *intel_dp = dev_priv->psr.enabled; + /* We have to make sure PSR is ready for re-enable + * otherwise it keeps disabled until next full enable/disable cycle. + * PSR might take some time to get fully disabled + * and be ready for re-enable. + */ + if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) & + EDP_PSR_STATUS_STATE_MASK) == 0, 50)) { + DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); + return; + } + mutex_lock(&dev_priv->psr.lock); intel_dp = dev_priv->psr.enabled; |