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authorDave Gordon2016-07-06 16:30:11 +0200
committerTvrtko Ursulin2016-07-06 17:24:46 +0200
commitab0e455bd0abe2b817c896b229b08045bafbdb94 (patch)
tree58e6320508ae68872da490ecf7ff37df806cb362 /drivers/gpu/drm/i915/intel_dp.c
parentdrm/i915: Group the irq breadcrumb variables into the same cacheline (diff)
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drm/i915: avoid wait_for_atomic() in non-atomic host2guc_action()
Rather than using wait_for_atomic() when chacking for a response from the GuC, we can get the effect of a hybrid spin/sleep wait by breaking it into two stages. First, spin-wait for up to 10us to minimise latency for "quick" commands; then, if that times out, sleep-wait for up 10ms (the maximum allowed for a "slow" command). Being able to do this depends on the recent patch 18f4b84 drm/i915: Use atomic waits for short non-atomic ones and is similar to the hybrid approach in 1758b90 drm/i915: Use a hybrid scheme for fast register waits (although we can't use that as-is, because that interface doesn't quite match what we need here). Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1467815411-21756-1-git-send-email-david.s.gordon@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
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