diff options
| author | Michal Wajdeczko | 2017-11-03 16:18:15 +0100 |
|---|---|---|
| committer | Chris Wilson | 2017-11-08 22:34:19 +0100 |
| commit | b814b0744a1434aa46c72bd02c3e9c8b1263f120 (patch) | |
| tree | 4490479661a16ec035977fdaf333bd9662b939b1 /drivers/gpu/drm/i915/intel_guc_fw.c | |
| parent | drm/i915/guc: Drop legacy workarounds from guc_prepare_xfer (diff) | |
| download | kernel-qcow2-linux-b814b0744a1434aa46c72bd02c3e9c8b1263f120.tar.gz kernel-qcow2-linux-b814b0744a1434aa46c72bd02c3e9c8b1263f120.tar.xz kernel-qcow2-linux-b814b0744a1434aa46c72bd02c3e9c8b1263f120.zip | |
drm/i915/guc: Simplify programming of GUC_SHIM_CONTROL
We can program GUC_SHIM_CONTROL register with all expected
bits without use of extra macro defined in fwif.h
v2: rebased without pre-prod code
v3: fixed typo
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171103151816.62048-4-michal.wajdeczko@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_guc_fw.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_guc_fw.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index a63b5cf7421a..69ba01599575 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -101,8 +101,13 @@ static void guc_prepare_xfer(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); - /* Enable MIA caching. GuC clock gating is disabled. */ - I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); + /* Must program this register before loading the ucode with DMA */ + I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES | + GUC_ENABLE_READ_CACHE_LOGIC | + GUC_ENABLE_MIA_CACHING | + GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | + GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | + GUC_ENABLE_MIA_CLOCK_GATING); if (IS_GEN9_LP(dev_priv)) I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); |