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| author | Arun Siluvery | 2016-01-18 16:59:36 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2016-01-19 20:37:55 +0100 |
| commit | f3272e7a7456240209e758d6a995acbae1d21e8e (patch) | |
| tree | 3781975c2f4240a1a6c4979a619db9c86e54dbd4 /drivers/gpu/drm/i915/intel_guc_fwif.h | |
| parent | drm/i915: Demote user facing DMC firmware load failure message (diff) | |
| download | kernel-qcow2-linux-f3272e7a7456240209e758d6a995acbae1d21e8e.tar.gz kernel-qcow2-linux-f3272e7a7456240209e758d6a995acbae1d21e8e.tar.xz kernel-qcow2-linux-f3272e7a7456240209e758d6a995acbae1d21e8e.zip | |
drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
In GuC submission mode, driver has to provide a list of registers to be
save/restored during gpu reset, make the max no. of registers value consistent
with that of the value defined in FW. If they are not in sync then register
save/restore during gpu reset won't work as expected.
Cc: Alex Dai <yu.dai@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453132776-22229-1-git-send-email-arun.siluvery@linux.intel.com
Reviewed-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_guc_fwif.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_guc_fwif.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index b4632f0bf7b2..1856a4740b83 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -370,7 +370,7 @@ struct guc_policies { #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 -#define GUC_REGSET_MAX_REGISTERS 20 +#define GUC_REGSET_MAX_REGISTERS 25 #define GUC_MMIO_WHITE_LIST_START 0x24d0 #define GUC_MMIO_WHITE_LIST_MAX 12 #define GUC_S3_SAVE_SPACE_PAGES 10 |