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| author | Michal Wajdeczko | 2019-05-27 20:36:05 +0200 |
|---|---|---|
| committer | Chris Wilson | 2019-05-28 11:07:12 +0200 |
| commit | 2d4ed3a988e6b1ff9729d0edd74bf4890571253e (patch) | |
| tree | 480b8b093cb2649ea58156427021c0fdb933b6b9 /drivers/gpu/drm/i915/intel_guc_reg.h | |
| parent | drm/i915/guc: New GuC interrupt register for Gen11 (diff) | |
| download | kernel-qcow2-linux-2d4ed3a988e6b1ff9729d0edd74bf4890571253e.tar.gz kernel-qcow2-linux-2d4ed3a988e6b1ff9729d0edd74bf4890571253e.tar.xz kernel-qcow2-linux-2d4ed3a988e6b1ff9729d0edd74bf4890571253e.zip | |
drm/i915/guc: New GuC scratch registers for Gen11
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190527183613.17076-10-michal.wajdeczko@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_guc_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_guc_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h index aec02eddbaed..d26de5193568 100644 --- a/drivers/gpu/drm/i915/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/intel_guc_reg.h @@ -51,6 +51,9 @@ #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4) #define SOFT_SCRATCH_COUNT 16 +#define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4) +#define GEN11_SOFT_SCRATCH_COUNT 4 + #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) #define UOS_RSA_SCRATCH_COUNT 64 |