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| author | Dave Airlie | 2019-02-11 04:41:53 +0100 |
|---|---|---|
| committer | Dave Airlie | 2019-02-11 04:41:59 +0100 |
| commit | 5ea3998d56346975c2701df18fb5b6e3ab5c8d9e (patch) | |
| tree | 07a9f5d74cc761cc73e66cefd0b7498341a8329f /drivers/gpu/drm/i915/intel_i2c.c | |
| parent | Merge tag 'drm/tegra/for-5.1-rc1' of git://anongit.freedesktop.org/tegra/linu... (diff) | |
| parent | drm/i915: Update DRIVER_DATE to 20190207 (diff) | |
| download | kernel-qcow2-linux-5ea3998d56346975c2701df18fb5b6e3ab5c8d9e.tar.gz kernel-qcow2-linux-5ea3998d56346975c2701df18fb5b6e3ab5c8d9e.tar.xz kernel-qcow2-linux-5ea3998d56346975c2701df18fb5b6e3ab5c8d9e.zip | |
Merge tag 'drm-intel-next-2019-02-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
UAPI Changes:
- Expose RPCS (SSEU) configuration to userspace for Ice Lake
in order to allow userspace to reconfigure the subslice config
per context basis. (Tvrtko, Lionel)
Driver Changes:
- Execbuf and preemption improvements including selftests (Chris)
- Rename HAS_GMCH_DISPLAY/HAS_GMCH (Rodrigo)
- Debugfs error handling fix for robustness (Greg)
- Improve reg_rw traces (Ville)
- Push clear_intel_crtc_state onto the heap (Chris)
- Watermark fixes for Ice Lake (Ville)
- Fix enable count array size and bounds checking (Tvrtko)
- MST Fixes (Lyude)
- Prevent race and handle error on I915_GEM_MMAP (Joonas)
- Initial rework for an full atomic gamma mode (Ville)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190208165000.GA30314@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_i2c.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_i2c.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 4f6dc8c94634..5a733e711355 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -823,7 +823,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; - else if (!HAS_GMCH_DISPLAY(dev_priv)) + else if (!HAS_GMCH(dev_priv)) /* * Broxton uses the same PCH offsets for South Display Engine, * even though it doesn't have a PCH. |