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| author | Ville Syrjälä | 2014-04-09 12:28:37 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-05-20 15:19:39 +0200 |
| commit | 0846697c6710a83bdacfe92b92c03288d87e24d9 (patch) | |
| tree | 1d6ec8aff0ec98aacca757f35d66b5658efe9213 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chv (diff) | |
| download | kernel-qcow2-linux-0846697c6710a83bdacfe92b92c03288d87e24d9.tar.gz kernel-qcow2-linux-0846697c6710a83bdacfe92b92c03288d87e24d9.tar.xz kernel-qcow2-linux-0846697c6710a83bdacfe92b92c03288d87e24d9.zip | |
drm/i915/chv: Implement WaDisableCSUnitClockGating:chv
This workaround is listed for CHV, but not for BDW. However BSpec notes
that on BDW CSunit clock gating is always disabled irrespective of the
relevant bit in the GEN6_UGCTL1 registers. For CHV however, such text
is not present in BSpec, so it seems safer to just set the bit.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7bf23c04dcbe..14cd13f7267f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5393,6 +5393,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev) /* WaDisableSemaphoreAndSyncFlipWait:chv */ I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); + + /* WaDisableCSUnitClockGating:chv */ + I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | + GEN6_CSUNIT_CLOCK_GATE_DISABLE); } static void g4x_init_clock_gating(struct drm_device *dev) |