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| author | Daniel Vetter | 2012-10-18 11:49:51 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2012-11-11 23:51:03 +0100 |
| commit | 4358a3748c39de3e66b6dc260af7a5ef785e120b (patch) | |
| tree | fe85b8c630dc0f203216ca665f46690dd2c21c2e /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: implement WaIssueDummyWriteToWakeupFromRC6 (diff) | |
| download | kernel-qcow2-linux-4358a3748c39de3e66b6dc260af7a5ef785e120b.tar.gz kernel-qcow2-linux-4358a3748c39de3e66b6dc260af7a5ef785e120b.tar.xz kernel-qcow2-linux-4358a3748c39de3e66b6dc260af7a5ef785e120b.zip | |
drm/i915: implement WaDisableRenderCachePipelinedFlush
Comment says for eaglelake/cantiga, but it's listed in the ilk table,
too. So apply it to both.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 59068beac3f2..f85043ca41b5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3382,6 +3382,10 @@ static void ironlake_init_clock_gating(struct drm_device *dev) I915_WRITE(_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED << 16 | _3D_CHICKEN2_WM_READ_PIPELINED); + + /* WaDisableRenderCachePipelinedFlush */ + I915_WRITE(CACHE_MODE_0, + _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); } static void gen6_init_clock_gating(struct drm_device *dev) @@ -3716,6 +3720,10 @@ static void g4x_init_clock_gating(struct drm_device *dev) if (IS_GM45(dev)) dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; I915_WRITE(DSPCLK_GATE_D, dspclk_gate); + + /* WaDisableRenderCachePipelinedFlush */ + I915_WRITE(CACHE_MODE_0, + _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); } static void crestline_init_clock_gating(struct drm_device *dev) |